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Georgia Tech Microelectronics Research CenterCMOS as a Research Platform
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| 1.3um N-well |
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NMOS ChemFET GT01
| Version 1.1 | |
| 1. | Thermal Oxidation |
| 2. | Level 1 Lithography: Source/Drain |
| 3. | Source/Drain Diffusion |
| 4. | Phosphorus Glass Removal |
| 5. | Field Oxidation/Drive-in |
| 6. | Level 2 Lithography: Gate and Contact Area |
| 7. | Gate Oxidation |
| 8. | Silicon Nitride Deposition |
| 9. | Level 3 Lithography: Contact area |
| 10. | Level 4 Lithography: Metal |
| 11. | Gold Deposition |
| 12. | PECVD Oxidation |
| 13. | Level 5 Lithography: Measurement contact |
| 14. | Spin on polyimide |
| 15. | Level 6 Lithography: opening for Conducting polymer |
| 16. | Conducting polymer |
| 17. | Level 7 Mask: Flip-chip Bonding |
MiRC, Georgia Tech
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