Georgia Tech Microelectronics Research Center CMOS as a Research Platform Baselines > 1.3um N-well > Furnace Assign.
Baselines 20um ChemFET 2.5um P-well 1.3um N-well Design Rules Mask Definition Process Flow Process Steps Results Furnace Assign. Research Training Services CMOS Group Documents Pictures Links Group Resources Search	CMOS Processing Furnace Assignment Furnace 1-1: Sinter Furnace 2-1: LTO/Implantation Anneal Furnace 2-2: Kooi, P-well drive, and dry oxidation Furnace 2-3: Gate oxide growth Furnace 2-4: Polysilicon deposition Furnace 3-1: N-type doping, Polysilicon doping (N-type) Furnace 3-2: P-type Doping Furnace 3-3: Padox, Well, Field (LOCOS) oxide growth Furnace 3-4: LPCVD silicon nitride Notes: Furnace 1-*: The old blue Lindberg furnaces Furnace 2-*: The refurbished Tyland furnaces Furnace 3-*: The new Tystar furnaces Tube Operating Temperature Ranges   Furnace 2-1 Furnace 2-2 Furnace 2-3 Furnace 2-4 Furnace 3-1 Furnace 3-2 Furnace 3-3 Furnace 3-4 Minimum: 950°C 950°C 950°C 588°C 900°C 1050°C 950°C 800°C Maximum: 950°C 950°C 950°C 620°C 950°C 1050°C 1150°C 850°C -James Zhou / January 14, 1999 MiRC, Georgia Tech
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